1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (semiconductor on insulator) MOSFET (metal oxide semiconductor field-effect transistor).
2. Description of the Background Art
FIG. 27 is a front sectional view of a conventional semiconductor device 151 forming the background of the present invention. In this semiconductor device 151, an insulator film 82 is formed on a semiconductor substrate 81, and an SOI layer 83 containing silicon as base material is formed on the insulator film 82. Namely, the semiconductor device 151 is formed as an SOI semiconductor device.
As shown in FIG. 27, an n-channel MOSFET is provided in the semiconductor device 151. An n-conductivity type source region 84, a p-conductivity type body region 86 and an n-conductivity type drain region 85 are provided in the SOI layer 83. The body region 86 is formed to be held between the source region 84 and the drain region 85. The source/drain regions 84 and 85 include nxe2x88x92-conductivity type low-concentration regions 88 and 89 and n+-conductivity type high-concentration regions 87 and 90 respectively.
A gate electrode 93 is opposed to the body region 86 through a gate insulator film 97. Side walls 94 are formed on side surfaces of the gate electrode 93 and the gate insulator film 97. A source electrode supplying a source potential Vs is connected to the source region 84, and a drain electrode supplying a drain potential Vd is connected to the drain region 85.
As shown in FIG. 27, a depletion layer 92 is formed in the body region 86 along p-n junctions. However, the SOI layer 83 is formed so sufficiently thick that the depletion layer 92 does not occupy the overall body region 86 but leaves a p-type semiconductor region 91 containing holes serving as carriers in a lower portion of the body region 86.
In other words, the SOI-type MOSFET provided on the semiconductor device 151 is formed as a MOSFET operating in a partially depleted mode (hereinafter referred to as a PD mode). The MOSFET operating in the PD mode has characteristics substantially equivalent to those of a bulk MOSFET since the depletion layer 92 does not reach the insulator film 82.
FIG. 28 illustrates a well-known semiconductor device 152 comprising a bulk MOSFET. This semiconductor device 152 comprises not a multilayer substrate including a semiconductor substrate 81, an insulator film 82 and an SOI layer 83, but a single semiconductor substrate 95. Source/drain regions 84 and 85 and a body region 86 are selectively formed in an upper portion of the semiconductor substrate 95.
As shown in FIG. 28, a wide p-type semiconductor region 96 containing holes is present under a depletion layer 92 in the bulk MOSFET. The bulk MOSFET is common in this point with the MOSFET operating in the PD mode, and hence the characteristics of the former are approximate to those of the latter.
In still another conventional semiconductor device 153 shown in FIG. 29, on the other hand, the thickness of an SOI layer 83 is by far smaller than that in the semiconductor device 151 shown in FIG. 27. In a MOSFET provided on the semiconductor device 153, therefore, a depletion layer 92 reaches an insulator film 82. In other words, the SOI-type MOSFET provided on the semiconductor device 153 is formed as a MOSFET operating in a fully depleted mode (hereinafter referred to as an FD mode).
The MOSFET (hereinafter also referred to as the MOSFET of the FD mode) operating in the FD mode advantageously obtains an ideal S factor dissimilarly to the MOSFET (hereinafter also referred to as the MOSFET of the PD mode) operating in the PD mode. The S factor, which is also referred to as a subthreshold coefficient, is defined as a slope S of a leading edge in a transition curve showing the relation between the logarithm of a main current Id and a gate potential Vg, as shown in FIG. 30. The transition curve more sharply rises as the S factor reduces, to provide desirable switching characteristics.
In the MOSFET of the FD mode, however, electrical resistance of the source/drain regions 84 and 85 is high due to the small thickness of the SOI layer 83, leading to inferior substantial characteristics as compared with the bulk MOSFET. In a step of forming contact holes for connecting main electrodes to the source/drain regions 84 and 85, the contact holes disadvantageously readily reach the insulator film 82 through the SOI layer 83 due to the small thickness thereof. In other words, it is difficult to connect the main electrodes to the source/drain regions 84 and 85.
When silicide layers are formed on surfaces of the source/drain regions 84 and 85 for reducing contact resistance between the source/drain regions 84 and 85 and the main electrodes, the silicide layers disadvantageously readily reach the insulator film 82 due to the small thickness of the SOI layer 83. The silicide layers are easy to separate when reaching the insulator film 82, as a matter of course.
On the other hand, the MOSFET of the PD mode having the thick SOI layer 83 causes no such problems of the MOSFET of the FD mode. However, the MOSFET of the PD mode cannot attain a small S factor advantageously obtained in the MOSFET of the FD mode. In the MOSFET of the PD mode, further, the p-type semiconductor region 91 located immediately under the depletion layer 92 is in a floating state to form an electrostatic capacitance between the p-type semiconductor region 91 and the gate electrode 93. Consequently, a gate threshold voltage disadvantageously fluctuates.
In addition, the p-type semiconductor region 91 stores holes and hence a parasitically formed npn bipolar transistor disadvantageously readily conducts. A leakage current increases following such conduction of the parasitic bipolar transistor.
A semiconductor device according to a first aspect of the present invention is provided with circuit elements in a semiconductor chip having an SOI layer, and comprises a MOSFET and a power supply part as the circuit elements. The MOSFET comprises a source region and a drain region selectively formed in the SOI layer and a body region held between the source region and the drain region, the thickness of the SOI layer is set at a value not fully depleting the body region under a floating condition and a condition supplied with the same potential as the source region, and the power supply part generates a voltage of a constant level and supplies the voltage between the source region and the body region in a direction for enlarging a depletion layer formed in the body region.
In the semiconductor device according to the first aspect of the present invention, the SOI layer is formed in a large thickness equivalently to the conventional MOSFET operating in the PD mode, whereby the resistance of the source drain and the drain region is suppressed low. Further, contact holes for connecting a main electrode to the source region and the drain region are easy to form. In addition, a semiconductor metal compound layer can be stably formed on surfaces of the source region and the drain region. Further, it is possible to drive the semiconductor device while applying a substrate bias without floating the body region or equalizing the potential thereof to that of the source region. Thus, the present invention relaxes or solves the problems of an instable gate threshold voltage and a large leakage current.
Further, no voltage for applying the substrate bias needs to be externally supplied, whereby no terminal needs to be provided for relaying the voltage for applying the substrate bias. In addition, wires in the semiconductor device can be reduced in length. Further, no specific power source needs to be prepared for using the semiconductor device, whereby the semiconductor device is convenient to use.
A semiconductor device according to a second aspect of the present invention is provided with a circuit element in a semiconductor chip having an SOI layer, and comprises a MOSFET as the circuit element. The MOSFET comprises a source region and a drain region selectively formed in the SOI layer and a body region held between the source region and the drain region, the thickness of the SOI layer is set at a value not fully depleting the body region under a floating condition and a condition supplied with the same potential as the source region, and the semiconductor device further comprises a terminal for being externally supplied with a voltage for relaying the voltage to the source region and the body region.
In the semiconductor device according to the second aspect of the present invention, the SOI layer is formed in a large thickness equivalently to the conventional MOSFET operating in the PD mode, whereby the resistance of the source drain and the drain region is suppressed low. Further, contact holes for connecting a main electrode to the source region and the drain region are easy to form. In addition, a semiconductor metal compound layer can be stably formed on surfaces of the source region and the drain region. Further, it is possible to drive the semiconductor device while applying a substrate bias without floating the body region or equalizing the potential thereof to that of the source region. Thus, the present invention relaxes or solves the problems of an instable gate threshold voltage and a large leakage current.
According to a third aspect of the present invention, the ratio L/W of the channel length L to the channel width W of the MOSFET is set smaller than a saturation start ratio.
In the semiconductor device according to the third aspect of the present invention, the ratio L/W is set smaller than the saturation start ratio, whereby the gate threshold voltage of the MOSFET is suppressed to a saturation value or below the same. Therefore, the semiconductor device can operate with a low power supply voltage. Further, it is possible to implement conversion from a PD mode to an FD mode by setting the voltage applied between the source region and the body region at the level saturating the gate threshold voltage, thereby improving the switching characteristics.
According to a fourth aspect of the present invention, the voltage is set at a level saturating a gate threshold voltage of the MOSFET.
In the semiconductor device according to the fourth aspect of the present invention, the body region is set at the level saturating the gate threshold voltage, whereby the MOSFET operates in an FD mode. Therefore, an ideal S factor is obtained to implement desirable switching characteristics. Further, the gate threshold voltage is saturated, whereby the semiconductor device can operate with a low power supply voltage. In addition, conversion from the PD mode to the FD mode is implemented by applying the voltage between the source region and the body region, whereby the gate threshold voltage is easy to set.
According to a fifth aspect of the present invention, the MOSFET further comprises a gate electrode opposed to the body region through an insulator layer and made of a mid-gap material.
In the semiconductor device according to the fifth aspect of the present invention, the gate electrode is formed by the mid-gap material, whereby the gate threshold voltage can be set relatively high. In other words, the gate threshold voltage can be pulled up to a desired level by properly selecting the mid-gap material for forming the gate electrode from various types of materials even if the gate threshold voltage is saturated. Thus, the degree of design freedom can be enlarged in relation to the gate threshold voltage.
According to a sixth aspect of the present invention, the ratio L/W of the channel length L to the channel width W of the MOSFET is set larger than a saturation start ratio.
In the semiconductor device according to the sixth aspect of the present invention, the ratio L/W is set larger than the saturation start ratio, whereby the gate threshold voltage can be increased due to a substrate bias effect.
According to a seventh aspect of the present invention, the semiconductor device further comprises a memory cell, a bit line connected to the memory cell and a sense amplifier connected to the bit line, and the MOSFET is connected to the bit line as a bit line load.
In the semiconductor device according to the seventh aspect of the present invention, the MOSFET having the gate threshold voltage increased by the substrate bias effect is employed as the bit line load, whereby the gain of the sense amplifier is improved.
A semiconductor device according to an eighth aspect of the present invention is provided with circuit elements in a semiconductor chip having an SOI layer, and comprises first and second MOSFETs and a power supply line as the circuit elements. Each of the first and second MOSFETs comprises a source region and a drain region selectively formed in the SOI layer and a body region held between the source region and the drain region, the thickness of the SOI layer is set at a value not fully depleting the body region of each of the first and second MOSFETs under a floating condition and a condition supplied with the same potential as the source region, both of the source region and the body region belonging to the first MOSFET are connected to the power supply line, the first MOSFET intervenes between the source region belonging to the second MOSFET and the power supply line, the body region belonging to the second MOSFET is connected to the power supply line, the ratio L/W of the channel length L to the channel width W of the first MOSFET is set larger than a saturation start ratio, and the ratio L/W of the channel length L to the channel width W of the second MOSFET is set smaller than a saturation start ratio.
In the semiconductor device according to the eighth aspect of the present invention, the voltage applied between the source region and the body region of the second MOSFET is higher than that in the first MOSFET. On the other hand, the ratio L/W is set larger than the saturation start ratio in the first MOSFET and smaller than the saturation start ratio in the second MOSFET respectively, whereby equality in the gate threshold voltages is improved between the first and second MOSFETs.
According to a ninth aspect of the present invention, either the channel lengths or the channel widths are set at the same value between the first and second MOSFETs.
In the semiconductor device according to the ninth aspect of the present invention, either the channel lengths or the channel widths are set at a common value while only the channel widths or the channel lengths are set at different values. Therefore, the semiconductor device is advantageously easy to design in pattern or the like.
According to a tenth aspect of the present invention, a semiconductor metal compound layer is formed on surfaces of the source region and the drain region.
In the semiconductor device according to the tenth aspect of the present invention, the semiconductor metal compound layer is formed on the surfaces of the source region and the drain region, whereby contact resistance between these regions and the main electrodes can be suppressed low. Further, the SOI layer is formed in a large thickness equivalently to the conventional MOSFET operating in the PD mode, whereby the semiconductor metal compound layer is hard to separate and stabilized.
Thus, an object of the present invention is to obtain a semiconductor device compatibly implementing the advantages of both conventional MOSFETs of the PD and FD modes.